Moore's law refers to an observation made by Intel co-founder Gordon Moore in 1965. Moore noticed that the number of transistors per square inch on integrated circuits had doubled every year since their invention. The small feature size allows hundreds of thousands, even millions, of devices to be fabricated on a wafer. However, the proximity of adjacent transistors may result in devices of the transistors suffering from poor metal layer isolation or result in leakage current between devices, which degrades performance. Integrated chips are fabricated through a plurality of processing steps (e.g., etching steps, lithography steps, deposition steps, etc.) upon a semiconductor wafer (e.g., a silicon wafer), followed by dicing the semiconductor wafer into separate integrated chips. In order to realize higher integration, simplify packaging processes, or couple circuits or other components, etc., in some cases, two or more wafers are bonded together before the dicing step, and circuits are fabricated on both sides of the wafer after thin down. Wafer level bonding is a promising technology for “More than Moore”, where added value is provided to devices by incorporating functionality that does not necessarily scale according to Moore's Law.